The present invention relates to semiconductor packages, and more particularly, to a thin profile semiconductor package with a chip mounted on a chip carrier.
In compliance with profile miniaturization of electronic products, semiconductor packages used as core elements in the electronic products are also preferably reduced in dimensions thereof.
Among thin profile semiconductor packages, LOC (lead-on-chip) semiconductor packages are exemplified herein. As shown in FIG. 8, U.S. Pat. No. 4,862,245 discloses a LOC semiconductor package 5P, in which a chip 50P is directly mounted onto a plurality of leads 51P, so that the leads 51P, in place of a die pad of a common lead frame, are used as a chip carrier for accommodating the chip 50P. However, due to difference in coefficient of thermal expansion (CTE) between the chip 50P and the leads 51P, during a high-temperature molding process or a reliability test such as a thermal shock test, the chip 50P suffers thermal stress from the leads 51P and tends to crack; this therefore damages quality and reliability of the fabricated semiconductor products.
The foregoing problem of chip cracking due to thermal stress, more frequently occurs in even more thin profile semiconductor packages such as TSOP (about 1 mm thick) or VTSOP (about 0.75 mm thick). Since a chip encapsulated in the TSOP or VTSOP semiconductor package often needs to be ground as thin as about 0.15 mm (6 mils), this accordingly reduces mechanical strength of the chip for resisting thermal stress. Therefore, when thermal stress is applied to the chip, it easily cracks the chip during a high-temperature molding process or a reliability test.
In order to solve the foregoing chip cracking problem, U.S. Pat. No. 5,901,043 discloses a semiconductor package with a dummy chip. As shown in FIG. 9, this semiconductor package 6P is characterized of mounting a dummy chip 61P on a chip 60P, wherein the dummy chip 61P is dimensionally smaller and substantially made of the same material as the chip 60P. The combined structure of the chip 60P and the dummy chip 61P can enhance mechanical strength of the chip 60P for resisting thermal stress, thereby reducing the occurrence of chip cracking in fabricating processes.
However, the foregoing semiconductor package 6P incorporated with the dummy chip 61P needs to use an adhesive for adhering the dummy chip 61P onto the chip 60P; this therefore increases complexity and costs in fabrication. Moreover, in a very thin profile TSOP or VTSOP semiconductor package, an encapsulant for encapsulating the chip 60P and the dummy chip 61P is also made thinner than normal. During molding, it may cause an encapsulating resin to flow at a slower speed above the dummy chip 61P than around sides of the dummy chip 61P, as shown in FIG. 10A. Uneven flow speed of the encapsulating resin easily leads to voids 8P formed at an end of the dummy chip 61P corresponding in position to a resin injection gate 7P, as shown in FIGS. 10B and 10C. Void formation may generate popcorn effect or damage to encapsulant appearance, thereby undesirably degrading the quality of fabricated semiconductor products.
Furthermore, during fabrication of a BGA (ball grid array) semiconductor package such as CSP (chip scale package), a chip has a CTE of about only 3 to 4 ppm, and CTEs of a substrate for accommodating the chip and of silver paste for adhering the chip onto the substrate are 18 ppm and 45 ppm, respectively. As shown in FIG. 11A, after the chip 90P is attached to the substrate 92P by means of the silver paste 91P, then in a temperature cycle of a molding process or a subsequent reliability test, as shown in FIG. 11B, the silver paste 91P and the substrate 92P generate compression stress (as indicated by arrows in the drawing) due to significant difference in CTE, which causes warpage to the substrate 92P. This compression stress accordingly produces tension stress applied on the chip 90P as indicated by arrows in the drawing of FIG. 11C, making the chip 90P easily crack and fabrication quality undesirably degraded.
A primary objective of the present invention is to provide a semiconductor package with a crack-preventing member, which can prevent the occurrence of chip cracking in a molding process.
Another objective of the invention is to provide a semiconductor package with a crack-preventing member, which can be cost-effectively fabricated by using simplified processes.
A further objective of the invention is to provide a semiconductor package with a crack-preventing member, which can prevent void formation in a molding process.
In accordance with the above and other objectives, the present invention proposes a semiconductor package with a crack-preventing member, comprising: a chip carrier; at least a chip mounted on the chip carrier and electrically connected to the chip carrier; at least a crack-preventing member formed at a predetermined position on the chip, for generating compression stress on the chip to counteract tension stress produced from the chip carrier on the chip in a molding process, so as to prevent the chip from cracking; and an encapsulant for encapsulating the chip and the crack-preventing member.
The crack-preventing member is not particularly limited in its shape, but it needs to generate the compression stress that can sufficiently counteract the tension stress produced from the chip carrier, so as to prevent the occurrence of chip cracking. The crack-preventing member is dimensionally designed not to be exposed to outside of the encapsulant and not to undesirably affect the overall thickness of the semiconductor package, wherein the crack-preventing member is preferably made of thermal contractible resin such as epoxy resin, and dimensioned to be one third or more in thickness of the chip, and more preferably in half thickness of the chip.